(1) Field of the Invention
The present invention generally relates to level conversion circuits which amplify input logic signals having small amplitudes (ECL levels) and generate output logic signals having large amplitudes (CMOS or TTL levels).
(2) Description of the Prior Art
FIG. 1 shows an ECL-CMOS level conversion circuit, which receives complementary ECL input signals IN1 and IN2 and outputs complementary CMOS output signals OUT1 and OUT2. Each of the ECL input signals IN1 and IN2 has a high (H) level of -0.8 V and a low (L) level of -1.8 V. Each of the CMOS output signals OUT1 and OUT2 has a high (H) level of 0 V and a low (L) level of -5 V.
The ECL-CMOS level conversion circuit shown in FIG. 1 is composed of two input terminals 1 and 2, two output terminals 9 and 10, two pMOS (p-channel Metal Oxide Semiconductor) transistors 5 and 6, and two nMOS (n-channel Metal Oxide Semiconductor) transistors 7 and 8. The sources of the pMOS transistors 5 and 6 are connected to a power supply line 3 set equal to 0 V, and the sources of the nMOS transistors 7 and 8 are connected to a power supply line 4 set equal to -5 V. The input signals IN1 and IN2 are applied to the gates of the pMOS transistors 5 and 6 via the input terminals 1 and 2, respectively, and output signals OUT1 and OUT2 are output via the output terminals 9 and 10 connected to the drains of the nMOS transistors 7 and 8, respectively.
As shown in FIG. 2A, the pMOS transistors 5 and 6 are OFF and ON, respectively, and the nMOS transistors 7 and 8 are ON and OFF, respectively, when the input signals IN1 and IN2 are maintained at -0.8 V and -1.8 V, respectively. In this case, the output signals OUT1 and OUT2 are maintained at -5 V and 0 V, respectively.
As shown in FIG. 2B, when the input signals IN1 and IN2 switch to -1.8 V and -0.8 V, respectively, the pMOS transistors 5 and 6 turn ON and OFF, respectively, and the nMOS transistors 7 and 8 turn OFF and ON, respectively. Hence, the output signals OUT1 and OUT2 switch to 0 V and -5 V, respectively. In this manner, the level conversion operation is executed.
FIG. 3 is a waveform diagram showing the operation of the level conversion circuit shown in FIG. 1 observed when a threshold voltage of each of the pMOS transistors 5 and 6 is -1.3 V and a threshold voltage of each of the nMOS transistors 7 and 8 is -4.0 V. When the output signals OUT1 and OUT2 switch to H and L levels from L and H levels, respectively, a period T1 is obtained during which both the pMOS transistor 5 and the nMOS transistor 7 are ON. During the period T1, through current passes through the pMOS transistor 5 and the nMOS transistor 7, and hence current which drives a load is reduced. As a result, it takes a long time for the output signal OUT1 to switch to H level from L level, and the level conversion circuit does not operate at a high speed.
Further, as shown in FIG. 3, a period T2 occurs during which both the pMOS transistor 6 and the nMOS transistor 8 are ON when the output signals OUT1 and OUT2 switch to the L and H levels from the H and L levels, respectively. During the period T2, through current passes through the pMOS transistor 6 and the nMOS transistor 8, and hence current which drives a load decreases. As a result, it takes a long time for the output signal OUT2 to switch to H level from L level.
Japanese Laid-Open Patent Application No. 3-55914 discloses a level conversion circuit intended to overcome the above disadvantages. A first nMOS transistor is connected between the nMOS transistor 7 shown in FIG. 1 and the power supply line 4, and a second nMOS transistor is connected between the nMOS transistor 8 and the power supply line 4. The gate of the first nMOS transistor receives the input signal IN1, and the gate of the second nMOS transistor receives the input signal IN2.
As has been described previously, the input signals IN1 and IN2 are ECL-level signals, and the L level thereof is approximately -1.8 V. Normally, an nMOS transistor has a threshold voltage (gate-source voltage) equal to 3.3 V. When the input signal IN1 switches to L level from H level, L level of -1.8 V is applied to the gate of the first nMOS transistor. Hence, the first nMOS transistor does not completely turn OFF, and a small amount of current passes through the pMOS transistor 5, the nMOS transistor 7 and the first nMOS transistor. As a result, the level conversion circuit shown in the above-mentioned Japanese application does not entirely eliminate the disadvantages of the level conversion circuit shown in FIG. 1.